# What's New in Xilinx ISE Design Suite 11

This file describes the new features in the Xilinx® ISE® Design Suite 11 software release. It contains the following sections:

Note: To disable this page from opening at ISE startup, from the Project Navigator workspace: Select Edit > Preferences > ISE General menu, and deselect "Open What's New document at startup."

- New ISE Design Suite Licensing and Product Configurations

- What’s New in Logic Design Tools

- What’s New in Embedded Tools and IP

- What's New in DSP Tools and IP

- What's New in CORE Generator and IP

- Technical Support

## New ISE Design Suite Licensing and Product Configurations

The following describes changes in the ISE Design Suite 11:

### Licensing for the ISE Design Suite is now managed by FLEXnet Publisher

- Xilinx software products join select Xilinx IP cores in using FLEXnet licensing

  - Allows customers to track their design tool and IP usage with an industry standard licensing scheme

  - Software and almost all FLEXnet licensed IP products can now be downloaded and licensed from a single website

    - Licensing through IP Product Lounges is no longer necessary

    - CAD-tool or customer license administrators now have improved ability to manage Xilinx software and IP licenses from a single web-location

    - IP licensing procedures now merged with software licensing flow, which reduces the time it takes to obtain an IP license from several days to just a few hours, or even minutes, in some cases

  - Floating and triple-redundant license servers now supported

    - One license shared by multiple users provides a cost-effective solution where multiple users can leverage a single seat

  - Node-lock licenses may use Host IDs from an Ethernet MAC address, hard-drive serial number, or dongle-based FLEXids

    - IP node-lock licenses formerly supported only Ethernet MAC addresses

### ISE Design Suite 11 offers configurations to match your design methodology

- ISE Design Suite: Logic Edition - complete toolset for your design and debug needs

  - Includes ISE Foundation™ design tool, ISE Simulator (ISim), PlanAhead™ design analysis tool, ChipScope™ Pro tool, ChipScope Pro Serial I/O Toolkit, and CORE Generator™ system

- ISE Design Suite: Embedded Edition - complete flow featuring logic and embedded capabilities

  - Includes ISE Design Suite: Logic Edition plus Embedded Development Kit (EDK) comprised of Xilinx Platform Studio (XPS) and Software Development Kit (SDK)

- ISE Design Suite: DSP Edition- complete flow featuring logic and digital signal processing (DSP) tools

  - Includes ISE Design Suite: Logic Edition plus System Generator for DSP and AccelDSP™ synthesis tool

- ISE Design Suite: System Edition -includes all software products in the ISE Design Suite for a complete system-level design solution

  - All tools in ISE Design Suite: Logic Edition plus EDK, System Generator for DSP, and AccelDSP synthesis tool

## What’s New in Logic Design

The following describes what’s new in ISE Foundation, ISE WebPACK™ software, ISim, PlanAhead, ChipScope Pro, and ChipScope Pro Serial I/O Toolkit:

### Reduced Runtime

- Synthesis runtime improvements

  - XST runs 1.6x to 2x faster, depending on design size and complexity

  - Improvements made to the low-level optimization phase

- Place and route runtime reduced by 46% across customer design suite

- Multi-threading support added for place and route on Linux

  - Leverage multiple processors or cores on a single machine

- SmartXplorer supports Load Sharing Facility (LSF) and Sun Grid Engine (SGE) compute farms on Linux

- Spawns flow compiles on multiple hosts for timing closure

- Compatible with existing compute farms (LSF and SGE)

- Provides an easy to use timing closure tool by experimenting advanced options and collating results

  - Leverages new netlist optimizations options

  - Available at the command line or via Project Navigator

- SmartXplorer also supports multiple processors and cores in a single machine on Windows

- SmartGuide™ technology tuning for faster runtimes

  - Focus placed on design preservation rather than timing improvement

- Completely redesigned ISim interface results in faster RTL simulation

  - Multi-processing is turned on by default in HDL compiler (fuse), which reduces compile time up to 2x

- SecureIP for Synopsys VCS-MX , Cadence NC-Sim and Mentor Graphics ModelSim/QuestaSim

  - Faster simulation runtimes by leveraging the latest encryption methodology

    - Simulation models for Hard-IP such as PowerPC® processor, MGT, and PCIe® standard leverage this technology

    - Seamless to setup and use as compared to SmartModels

### Usability Improvements

- Project Navigator – improved look and feel, usability, and responsiveness

  - Improved direct access to ISE applications

  - Improved tool integration with automatic handling of source and constraint files from System Generator for DSP, XPS, and CORE Generator system

  - Support for ASCII project files for easier source control and direct user editing

  - Streamlined process tree and Design Summary make it easy to find tools and reports

  - Flexible window layouts allow you to customize Project Navigator to meet your needs

- PlanAhead integration with Project Navigator

  - PlanAhead is now the single tool for floor planning and pin planning, replacing Floorplanner and PACE

  - PlanAhead is launched directly from within Project Navigator

  - PlanAhead constraints are automatically saved back to ISE project User Constraint File (UCF)

- Full PlanAhead features and functionality available to all ISE users

- ChipScope Pro integration within PlanAhead

  - Tighter integration allows users to insert ChipScope debug cores from within PlanAhead

    - ChipScope cores can be floorplanned with the rest of the design

    - Existing ChipScope core instances are automatically recognized

  - Tcl scripting supported for ChipScope VIO core

  - ChipScope Analyzer improvements

    - Bus creation and modification has been improved

    - Inserter project files (CDC) can be linked to bit files for automated signal annotation

- Easier pin planning in ISE with integrated PinAhead technology

  - Supports both pre- and post synthesis phases

  - Allows part/package migration

  - Improved design rule checks (DRC) and simultaneous switching noise (SSN) checks

- Enhanced design-oriented IBIS files

  - IBISWriter now supports DCI and differential I/O standards

- New RTL / Technology Viewer with debug features

  - Faster schematic rendering

  - New features allow for extraction of logic cones and hiding contents

- Timing Analyzer usability improvements

  - Component switching limits are now checked during place and route as well as timing analysis

  - Ability to specify multiple parameters for clock and I/O analysis: duty cycle, input jitter, valid duration, data arrival, clock edge/phase, etc

  - Link to DataSheet Delay names directly from timing reports for all architectures

  - Cross probing to FPGA Editor, including the complete clock path for offset constraints

  - Ability to print only selected section of timing reports

- ISim GUI improvements

  - A new static waveform viewer is available to open static simulation

  - Crisp, new look and feel

  - Improved scrolling and zoom features

  - New ruler tool to ease measuring capabilities

  - Support for virtual buses

  - Ability to add copies of signals into the same waveform

- PROM File Formatter redesigned

  - Single-pane interface shows all configuration data in one view

  - Built-in help explains each option and setting

### Power Optimization

- Dynamic power reduction

  - 10% dynamic power reduction from place and route

  - Re-synthesis to minimize element switching on critical cones of logic (based on VCD or SAIF activity file)

  - Placement to minimize use of vertical clock spines

  - Clustering of high activity elements

  - Clock gating in MAP

- Improved power estimation and analysis

  - Vectorless power estimation

  - Improved power analysis

    - Tune worst-case power estimation such that worst case will not under-estimate

    - Xilinx Power Estimator (XPE) provides an estimate of dynamic power reduction when using low power switches

  - Switching Activity Interface Format (SAIF) files can be generated by ISim

### Reduced Memory Usage

- 30% reduction in memory for synthesis and place and route

- Improved Project Navigator responsiveness and memory efficiency

- Redesigned ISim interface reduces memory usage

### Design Optimization Improvements

- New goal-based optimization

  - Global optimization during place and route can be run in one of three modes: power, speed or area

- XST gives improved area and performance

  - Better handling of BRAMs in byte-write enable mode

  - Improved processing of dual-port BROMs

  - Better register absorption for DSP blocks

- Performance tuning has been improved for Virtex®-5 devices

### User Assistance Improvements

- ISE Help

  - Easier to find information

  - Reorganized based on steps in the design flow

  - New sections added to assist with analyzing and optimizing design implementation results

- ISim Help

  - Content rewritten to follow the software flow

- ISim User Guide

  - The ISim User Guide is a new addition to the user assistance collection. It contains the same content as ISim Help and is available both in the software and on the Xilinx website.

- Command Line Tools User Guide

  - Formerly known as the Development System Reference Guide, the document had a name refresh and is now the Command Line Tools User Guide. The document provides an overview of the Xilinx development system and information on command line implementation tools and options for both FPGA and CPLD devices.

- Documentation Updates

  - Updates to the ISE books and online help are now delivered via the XilinxUpdate utility in the ISE software. To ensure you have the most recent copy of the ISE documentation installed on your system, run the XilinxUpdate utility using the Help > XilinxUpdate menu command. You can also get the latest documentation update in the Xilinx Download Center at www.xilinx.com/download.

## What’s New in Embedded Tools and IP

The following describes what’s new in SDK, EDK, XPS, and embedded IP:

### Software Developers Kit (SDK)

- SDK is now available as a standalone development tool

  - The larger ISE Design Suite installation is no longer required, significantly reducing required installation space

  - SDK now imports the hardware platform information from XPS

  - EDK contains one seat of SDK and one seat of XPS

- SDK enhancements:

  - No requirements for location of SDK workspace

  - Automatically recognizes changes to hardware specification, and automatic resynch of software projects

  - Support for multiple software platforms and board support package (BSP) projects in a single workspace

  - Enhanced C/C++ Projects View

  - Simplified BSP configuration dialogs

  - Integrated creation of test programs

  - Enhanced list of test programs

  - Retargeting of software projects to different hardware systems

  - Support for software repositories

  - Integrated FPGA download capability

  - Safe mode debugging to trap unhandled exception conditions

  - Can now set breakpoints in program startup routines

  - Enhanced user documentation and built in cheat sheets (tutorials)

  - Datasheets for IP and drivers can be accessed via the design report included in the hardware handoff files

  - Ability to stop MicroBlaze™ processor v7.20.a when in a blocked state

  - Command line XMD now supports directory auto-completion and history

  - JRE version updated to 1.5

  - Enhanced import of software projects

  - System Generator integration support with SDK for software development

  - lwIP library updated

### Xilinx Platform Studio (XPS)

- XPS enhancements:

  - Base-system builder (BSB) creation of dual-PPC, dual MicroBlaze, and mixed processor system

    - Automation of dual processor designs

    - Enables unique capabilities of using FPGAs with embedded processors

    - Exploits dual PPC Virtex devices

    - Enable higher system performance levels

  - New start up page for easier navigation of documentation and support pages

  - Ability to explicitly set simulator path to match ISE

  - New project archiver

  - Automation to create local copies of pcores

  - Integrated design summary page

  - New "Export Hardware Design to SDK" capability

  - Integration of MIG PHY generation for MPMC

- Easy way to filter out bus interfaces and ports in System Assembly view to enable focus on specific portions of designs

- Numbers associated with messages and ability to filter messages in Design Summary view

- Address tab in System Assembly view shows processor instance specific address map

- More instant feedback and DRCs within XPS during design modification

- Comprehensive change log for embedded IPs spanning over multiple-versions of a given IP

- Embedded software development features have been deprecated in XPS and will be removed in future release

- Changes in the Clock Generator GUI will now automatically update resulting system changes

### EDK/ISE Integration Improvements

- Improved synchronization eliminates unnecessary recompilations of XPS projects

- Automatic incorporation of UCF constraints for embedded module into FPGA implementation flow

### Embedded IP

- MicroBlaze specific

  - Write-back caches

  - New atomic test and set instructions

  - Debug enhancements

- MultiPort Memory Controller (MPMC)

  - Debug registers, provides software control over PHY

  - MIG 3.0 PHY support

  - MIG PHY generation now integrated in XPS

- MicroBlaze and MPMC optimizations

  - Dual, smaller footprint Cache Link interface

  - Direct Microblaze access to MPMC control registers

- OPB and PLBv34 cores are deprecated (except bridges and buses)

- xps_ll_temac

  - Reduced resources - now uses fewer BUFGs and BRAMs

  - Improved RX performance through more efficient FIFO full management

- plbv46_pcie

  - Split out block plus wrapper into encrypted helper core

  - Top level is now open source

  - Added support for x4 and x8

- usb2_device core

  - Smaller footprint

  - Faster performance

- See individual core history files for more updates

## What’s New in DSP Tools and IP

The following describes what’s new in System Generator, AccelDSP, and DSP IP:

Both System Generator for DSP and AccelDSP support MATLAB® R2008 software.

### System Generator for DSP

- Linux support

  - Red Hat Enterprise Linux 4 WS (32 and 64-bit)

- Integration with SDK

  - System Generator can launch SDK to modify software running on an embedded processor

- IP lifecycle

  - Old versions of versioned IP have been superseded

  - Warning message generated for any Xilinx IP core that is not the latest version

  - Summary report generated for designs that contain IP that is not the latest version

- Updated design examples

- New and updated examples using the latest IP and targeting the latest devices

- Integration with XReport

  - XReport can be launched directly from System Generator

- New/Updated IP

  - New blocks with support added for Virtex-5 and extended Spartan®-3A devices - CORDIC 4.0, Complex Multiplier 3.0

  - Updated basic building blocks to version 11.0 - Adder Subtractor, Accumulator, Binary Counter, Multiplier, Addressable Shift Register

  - Updated memory blocks to use Block Memory Generator 3.1, Distributed Memory Generator 4.1 and FIFO Generator 5.1 –Single port RAM, Dual Port RAM, ROM, FIFO, Shared Memory, To FIFO and From FIFO

### AccelDSP Synthesis Tool

- Higher performance design examples

  - Updated to target latest silicon and implement at higher frequencies

- Enhanced Fixed-Point Report to aid in achieving higher quality of results (QoR)

  - New tabs can be sorted to show details on largest operators, largest arrays, and architecture information

- LogiCORE™ system performance enhancements

  - LogiCORE usage is now the default for the VHDL flow

  - New support for adder and subtractor

  - New GUI support for LogiCORE parameters

- New support to add more than one register to all inputs and outputs for higher performance

- Memory map enhancements

  - New option "ram_threshold" to automatically map arrays to RAM

  - "sp_sync_ram" and "sp_sync_rom" have been removed and replaced with "dp_sync_ram"

  - New option "array_access_guard" to control scheduling optimizations

- Tab and references for AccelWare™ reference design have been removed

  - All MATLAB functions previously supported via AccelWare are still supported via AccelDSP

## What's New in CORE Generator and IP

The following describes what’s new in CORE Generator and IP cores:

- New IP cores

- Math functions

  - Multiply Adder v2.0 - performs multiplication of two operands and adds (or subtracts) the full-precision product to a third operand using Xtreme DSP™ solution slices

  - Multiply Accumulator v2.0 - accepts two operands, a multiplier and a multiplicand, and produces a product that is added (or subtracted) to the previous result using Xtreme DSP slices

- Video and image processing

  - Color Correction Matrix v1.0 - a highly optimized constant coefficient matrix multiplier core using Xtreme DSP slices for correcting color in a video data stream

  - Color Filter Array Interpolation v1.0 - a high quality hardware block used for interpolating between RAW sensor data and the RGB color domain

  - Defective Pixel Correction v1.0 – IP optimized for "real-time" operation for automatic detection and correction of defective pixel with interpolated values based on neighboring pixels

  - Gamma Correction v1.0 - provides customers with a fully tested and optimized hardware block for manipulating the values on a per pixel basis for gamma adjustment

  - Image Processing Pipeline v1.0 - dedicated hardware core to automatically generate an image from a CMOS/CCD sensor from a given set of parameters which includes a wide range of features and optimizations

  - Video Scaler v1.0 - a high-quality scaling solution for customers implementing designs ranging from polyphase to linear interpolation for up and down scaling

- IP core updates

- A comprehensive listing of cores that have been updated in this release can be viewed at www.xilinx.com/ipcenter/coregen/11_1_datasheets.htm

- For more information see www.xilinx.com/ipcenter/coregen/updates_11_1.htm

- New CORE Generator features

  - IP catalog enhancements

    - IP catalog visible within Core Generator before opening a project

    - Enhanced keyword search lists results both by functional category or by name

    - IP core scheduled to be “Superseded” by newer versions and cores scheduled to be “Discontinued” can be viewed by selecting “All IP Versions”

    - IP cores supported for selected device family can be viewed by selecting “Only IP Compatible with chosen part”

- Enhanced IP output

  - Generation of ISE project files to facilitate integration and management of IP cores in Project Navigator

  - Selected video and image processing cores generate “EDK Pcore” to facilitate integration and management of IP cores within XPS projects

- Automated core upgrade to latest version capability is available for the following IP cores: Adder Subtracter, Accumulator, Binary Counter, Block Memory Generator, Complex Multiplier, CORDIC, Multiplier and RAM-based Shift Register

- Capability to allow regeneration of all project IP cores with different project settings than were originally used to generate the core

## Technical Support

For Technical Support Issues, visit www.xilinx.com/support where features such as the Answers Database and User Forums may help to resolve your issue. If your issue can not be resolved on the support site, a WebCase can be created and a Technical Support engineer can further assist you.

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